Senior Digital Design

DIGITAL DESIGN ENGINEER

The Group  

The Joint Development Team (JDT) is a small, independent, cross-disciplinary group whose charter is to accelerate the development of key components, systems, algorithms, and techniques necessary to advance the state of the art in targeted areas and to collaborate with focused product development teams to get these advances to the marketplace. Current and future research areas include advanced medical devices, energy metering and fault detection, high-speed imaging, security electronics, ultra-precision references and data converters.  

The group is led by Analog Devices Fellow JED Hurwitz, a pioneer in CMOS imaging, recognized expert in ultra-high precision, and of broad industrial experience. The group culture aims to foster a challenging, exciting, and supportive environment.  

The team members must be comfortable working on a wide variety of products and technologies in a fast-paced and agile environment and will be exposed to various groups across the corporation’s many sites through all stages of the development cycle.  

The Role 

The P3 Digital Design Engineer contributes to RTL design, subsystem implementation, and mixed-signal integration of digital logic blocks under the mentorship of senior designers. Work spans RTL creation, verification collaboration, and supporting implementation flows. The engineer is expected to develop skills related to digital verification. The engineer may switch between design and DV roles depending on project needs once sufficiently trained. 

Key Responsibilities 

• Write RTL for digital blocks based on specifications. 

• Perform lint, CDC analysis, and support DFT integration. 

• Assist in writing functional testcases and simple UVM components. 

• Collaborate with DV engineers for coverage closure and bug resolution. 

• Support AMS co‑simulation and integration with analog blocks. 

• Work with physical design teams on synthesis and timing. 

• Train and develop skills in digital design verification 

Minimum Qualifications 

• BS or MS in ECE, EE, CpE, or equivalent. 

• 2–5 years digital design experience, or strong NCG background. 

• Proficiency in SystemVerilog/Verilog; familiarity with UVM preferred. 

• Experience with scripting languages (Python/Perl/TCL). 

• Basic understanding of AMS modeling and mixed‑signal flows is a plus. 

• Strong analytical, problemsolving, and communication skills. 

• Capable of performing independent research and self study