About the Role
We're looking for a Senior Emulation Engineer to join our hardware verification team. In this role, you'll own the emulation environment for our next-generation NPU — from platform bring-up to full-system integration — and play a critical part in getting silicon right before tape-out. You'll work across time zones with engineers in Korea and the US, and have a direct impact on the quality and schedule of our most complex SoCs to date.
What You'll Do
NPU Emulation & Bring-up: Bring-up of next-generation NPUs on emulation platforms. Root-cause complex system-level test failures and resolve emulator environment challenges.
Emulation Interface & Memory Integration: Enable full-system NPU testing by integrating and bringing up high-speed protocol models (PCIe, Ethernet) and advanced memory subsystems (HBM/DDR) within the emulation environment.
What We're Looking For
Emulation Platform Expertise: Extensive, hands-on experience in developing, compiling, and deploying large-scale emulation models using industry-leading platforms such as Synopsys ZeBu and Cadence Palladium.
Domain Knowledge: Deep technical understanding of AI accelerator architectures (NPU), along with expertise in one or more of the following: interconnect buses, high-speed I/O protocols (PCIe, Ethernet), and advanced memory interfaces (LPDDR, HBM).
Strategic Verification Leadership: Demonstrated ability to define comprehensive emulation strategies, formulate detailed test plans, and drive verification execution for large-scale, complex SoCs.
Core Qualifications
8+ years of industry experience in hardware emulation or system-level verification.
Bachelors or Masters degree in Electrical Engineering, Computer Engineering, Computer Science, or a related engineering field.
Strong domain knowledge of AI accelerator architectures (NPU), interconnect buses, high-speed I/O protocols (PCIe, Ethernet), and advanced memory interfaces (LPDDR, HBM).
Ability to take initiative and work independently in a cross-regional environment, collaborating effectively across different time zones (Korea and US).
Bonus Points
Track record of writing production-grade, meticulous test plans
Strong foundational knowledge of networking protocols
Contact
FuriosaAI designs high-performance, power-efficient AI accelerators (NPUs) used in data centers for computer vision, GenAI, LLMs, and demanding workloads.
Key team members
Auro Tripathy
Oliver Libaw
Nuno Lopes
Eliezer Lubitch
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