Senior Manager, VLSI Design Engineering ( IO Design (LVCMOS, HVCMOS, DDR, LVDS)) with 15+ Years of experience

Job Description

We're looking for an experienced Senior Manager, VLSI Design Engineering to join our organization in Bangalore, India. In this role, you will lead a team of talented design engineers and drive the development of cutting-edge semiconductor solutions. You will be responsible for overseeing the entire VLSI design lifecycle, from concept through production, while maintaining the highest standards of quality and innovation. The ideal candidate will combine deep technical expertise with strong leadership capabilities, demonstrating a detail-oriented and analytical approach to complex engineering challenges.

• Lead team of experienced IO Design Engineers
• Strategic development of next generation IO for scaling speed
• Build Best in Class IP Design
• Handling Business Unit communication on all IO Roadmap, RMA, FA
• Drive End-End IO Design capability and execution till Silicon to Productization
• Manage project timelines, budgets, and resource allocation while maintaining organizational objectives
• Drive innovation in VLSI design techniques and stay current with emerging technologies and industry trends
• Evaluate and recommend EDA tools and design automation solutions to improve team efficiency
• Perform power analysis and optimization to meet performance and energy efficiency targets
• Communicate technical progress and strategic recommendations to senior management and stakeholders

Qualifications

 

• Bachelors/Masters degree in Electronics & Telecommunication/Electrical engineering (VLSI Design)
• Extensive Hands-on design experience in IO Design (LVCMOS, HVCMOS, DDR, LVDS)
• 15+ years of Experience on handling IO designs, projects working with BU, Stake holders. 5+ years of leading a high performance team is desirable.
• NAND Flash Design knowledge is plus
• Expertise in ESD, Power bus, Floor plan, Layout guidelines
• Expertise, knowledge of advanced DDR algorithms: Training modes and DFE/CTLE/Compensation Techniques, Clock skew techniques
• Management and Lead experience to handle Team of IO engineers
• Experience in working with cross geo, cross team functions and stake holder management
• Expertise with package/board/Power integrity /signal integrity constraints is a plus.
• Strong communication skills & circuit design knowledge is preferred.
• Tool knowledge: spice tools: finesim, hspice & other flows
• Background in AI/ML chip design or emerging semiconductor technologies is a plus
• Experience coordinating with cross-functional teams including manufacturing, quality, and product engineering is desirable

Additional Information

All your information will be kept confidential according to EEO guidelines.