Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Job Description

We are seeking a Senior Foundry Engineer, Silicon Technology to support foundry engagement, silicon-to-model correlation, tapeout readiness, and yield improvement for advanced semiconductor products. This person will work closely with internal design, CAD layout, product engineering, test, reliability, operations teams and external foundry partners to identify risks, assess product impact, and drive timely resolution of process, PDK, model, DRC/DFM, and silicon-related issues.

Responsibilities Include

Silicon, process and yield correlation

Analyze process inline data, silicon test data, process drift and process correlation data
Fine tune processes to optimize power, performance and yield
Help identify process related contributors to parametric drift, yield loss, leakage, reliability risk
Work with foundry and internal teams to investigate yield issues and process excursions
Perform layout analysis where needed to understand process sensitivity, failures

Tapeout and DFM support

Support product tapeouts, tapeout readiness reviews from a PDK, DRC/DFM, device model and reliability perspective
Run or coordinate DFM checks on products and summarize findings for design and layout teams
Coordinate between foundry and physical design teams to disposition waivers taking performance, leakage, manufacturability and reliability in mind
Document known PDK, model, DRC, DFM or process risks before tapeout
Maintain an internal PDK qualification database across foundries and process nodes to reduce tapeout risk from unnoticed PDK or model changes

Foundry and PDK support

Support technical interactions with foundry partners on PDK, device models, process assumptions, design rules, DRC/DFM decks and reliability collateral
Track PDK versions, model updates, DRC/DFM runset changes, and foundry signoff recommendations
Compare PDK changes across versions and summarize potential design, layout, model or signoff impact

Device model and circuit model evaluation

Validate model behavior across voltage bias, temperature, process corners, and relevant operating conditions
Compare silicon measurements against SPICE/model predictions and help identify model gaps

Basic Qualifications:

B.S or M.S in Electrical Engineering, Material science, Semiconductor engineering or a related technical field
5+ years of experience in semiconductor device engineering, foundry interface, silicon technology, process integration, yield/process correlation

Required Experience:

Working knowledge of semiconductor process flows, device physics, manufacturability, reliability and yield drivers
Experience supporting tapeouts, PDK validation, models, DRC/DFM, silicon bring up
Experience analyzing silicon, wafer-level, process monitors, product test, characterization, or reliability data
Prior experience at a foundry, IDM, fabless semiconductor company or a PDK/enablement organization
Familiarity with SPICE models, process corners, device behavior, layout effects and silicon-to-model correlation
Ability to communicate technical issues clearly across design, CAD, layout, test, products engineering and external foundries
Familiarity with using TSMC as a foundry

Preferred Experience:

Experience with advanced FinFET, gate-all-around/nanosheet technologies and BiCMOS technologies
Experience with SRAM, analog/mixed signal, RF, Serdes, low power design constraints
Experience benchmarking foundry nodes using spice models on representative circuits
Experience using foundry models to simulate junction breakdowns, SOA, ESD, aging, reliability or device operating limits

Senior Foundry Engineer, Silicon Technology

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Astera Labs