About Neurophos

The demand for new datacenters and AI compute is rapidly outpacing the planet's energy capacity. Digital solutions are hitting a power wall as we approach the physical limits of traditional silicon. Conquering this bottleneck isn’t about bigger chips or more of them; it means rethinking the fundamental architecture. The industry's current path isn’t going to meet the need, so we took a different approach.

Instead of traditional electronic circuits, we use silicon photonics and an active, programmable metasurface to perform matrix multiplications at the speed of light. Our optical cells are 10,000x smaller than traditional photonic components, enabling unprecedented density. By using photonics instead of electricity, our chips become more efficient as they scale. This architecture will deliver up to 100 times the energy efficiency of existing solutions while significantly improving performance for large-scale AI inference.

We’ve assembled a world-class team of industry veterans and recently raised a $110M Series A led by Gates Frontier. Participants include M12 (Microsoft’s Venture Fund), Carbon Direct Capital, Aramco Ventures, Bosch Ventures, Tectonic Ventures, Space Capital, and others. We have also been recognized on the EE Times Silicon 100 list for several consecutive years.

Join us and shape the future of computing!

Position Overview

Neurophos is seeking a hands-on Senior Manager of OPU Product Board Design to own the full board design function across two tightly coupled domains: conventional computer hardware board design and optoelectronics board integration. This is a senior technical leadership role with direct ownership of all OPU product PCBs — from architecture and schematic capture through layout, bring-up, and production release.

The right candidate will bring deep personal hands-on experience in high-speed digital board design and a working understanding of optoelectronic circuit integration (laser drivers, TIAs, high-speed DAC/ADC, metasurface/SLM drive electronics, silicon photonics IC interfaces). You will hire and develop engineers with specialized expertise in each domain, but you will retain overall technical and program ownership across both. You will partner closely with optical, mechanical, ASIC, firmware, and test engineering teams to ensure that board-level designs meet the demanding signal-integrity, power-delivery, thermal, and optical-drive requirements of the OPU platform.

Location

San Jose, CA or Austin, TX. Full-time onsite position.

Key Responsibilities

• Board Design Ownership

  • Own end-to-end PCB development for all OPU product boards, including host interface carrier boards, silicon photonic IC interposers, metasurface/SLM driver boards, and subsystem evaluation platforms.

  • Define board architecture, layer stack-ups, and design rules for high-speed digital interfaces (PCIe Gen 5, UCIe, DDR5) and high-fidelity analog/optoelectronic drive circuits on the same or adjacent boards.

  • Lead schematic capture and layout reviews, enforcing DFM, DFT, and signal integrity standards across both digital and optoelectronic board domains.

  • Drive board-level bring-up, debug, and characterization for complex mixed-signal systems; establish repeatable verification methodologies covering both electrical and optical functional tests.

  • Maintain schematic block libraries, footprint libraries, and simulation models that span digital, analog, and optoelectronic component families.

  Optoelectronics Board Integration

  • Lead board-level integration of silicon photonic ICs, laser driver ICs, transimpedance amplifiers (TIAs), and high-speed DAC/ADC circuits that interface directly with the OPU optical engine.

  • Collaborate with optical and optomechanical engineers to translate optical system specifications into concrete PCB design requirements.

  • Define and execute board-level qualification plans for optoelectronic subsystems, including eye diagram measurements, BER characterization, and optical power budget validation.

  • Stay current on silicon photonics packaging trends and assess their impact on future OPU board architectures.

  People & Team Building

  • Recruit, onboard, and develop a team of board design engineers.

  • Define team roadmap and resource allocation across multiple concurrent board programs.

  • Provide technical mentorship, set clear performance goals, and conduct regular reviews to support each team member's growth.

  • Foster a design culture that values simulation-first rigor, thorough design reviews, and systematic root cause analysis.

  Cross-Functional Collaboration & Vendor Management

  • Interface with ASIC, firmware, test engineering, and system integration teams to ensure board designs support automated functional test, KGD workflows, and in-system diagnostics.

  • Manage PCB fabricators, contract manufacturers, and component suppliers; drive NPI schedules, DFM feedback loops, yield improvements, and cost-reduction initiatives.

  • Communicate board program status, critical path risks, and resource needs to engineering leadership clearly and on a regular cadence.

Qualifications

• Bachelor’s or master’s degree in electrical engineering or a closely related discipline.

• 10+ years of hands-on PCB and hardware engineering experience, with at least 3 years in a people management or technical lead role.

• Deep expertise in high-speed digital PCB design — including stack-up optimization, differential pair routing, impedance control, and PDN design — for SerDes rates of 25G and above (PCIe Gen 4/5, 56G/112G SerDes).

• Hands-on experience with optoelectronic board design: laser driver ICs, TIA circuits, high-speed DAC/ADC interfaces, or silicon photonics IC integration at the board level.

• Proficiency with industry-standard EDA toolchains (Cadence Allegro/OrCAD, Altium, or equivalent) and SI/PI simulation tools (HyperLynx, Sigrity, or equivalent).

• Demonstrated track record bringing complex multi-layer boards (16L+) from schematic through NPI and into volume production.

• Strong background in power delivery design for high-power ASIC, SoC, and photonic IC loads, including multi-phase VRM design, LDO selection, and EMI mitigation.

• Proven ability to hire, develop, and retain specialized engineering talent in a fast-paced startup environment.

• Excellent written and verbal communication skills; able to clearly represent the board program's status and risks to technical peers and executive leadership.

Preferred Skills

• Experience with metasurface or spatial light modulator (SLM) drive electronics and associated precision analog/mixed-signal board design.

• Familiarity with silicon photonics IC packaging approaches: co-packaged optics, flip-chip, or photonic wire bonding integration.

• Background in thermal management design for high-power-density optical and electronic assemblies.

• Experience with FMEA, design reviews (CDR/PDR), and NPI processes in a hardware startup or semiconductor environment.

• Exposure to PLM systems (Arena, Agile, Windchill) and engineering change order (ECO) workflows.

• Background in AI/ML hardware, optical communications, or photonic integrated circuit (PIC) product development.

What We Offer

This is an opportunity to play a pivotal role in an innovative startup redefining the future of AI hardware. Work on a game-changing technology at the intersection of photonics and AI as part of a collaborative and brilliant team. You’ll contribute to a platform that redefines computational performance and accelerates the future of artificial intelligence. Come help us bring this transformative technology to the world.

Benefits

Join a team that invests in your future and your well-being. At Neurophos, we offer:

• 100% coverage of base health plan premiums for you and your dependents, plus HSA contributions.