Staff/Senior Staff Power Integrity Engineer - Power Delivery

About Us

Powerlattice is a well-funded semiconductor start-up company backed by well-known large Silicon Valley VCs. The company is working on the industry’s groundbreaking chiplet solution for a fundamental shift in how high-performance chips get powered, paving the way for the next generation of AI and advanced computing.

About the Role

We’re a fast-moving startup building the foundation for next-generation AI compute. We're seeking a highly experienced Staff / Sr. Staff Power Integrity Engineer to lead the architecture, analysis, and optimization of next-generation advanced power delivery chiplet solutions for high-performance computing, AI accelerators, networking, and heterogeneous integration platforms.

In this role, you will drive end-to-end power integrity (PI) methodology and execution across silicon, package, interposer, and system domains for advanced multi-die/chiplet architectures. You will collaborate closely with architecture, package, silicon, signal integrity, thermal, CAD, and product engineering teams to deliver robust and scalable power delivery networks (PDNs) for cutting-edge technologies.

What You’ll Do

• Drive chip-package-system co-design for optimal power delivery and decoupling strategies.

• Lead power integrity architecture and implementation for advanced chiplet-based products and heterogeneous integration platforms.

• Develop PI design guidelines, methodologies, and signoff criteria for high-current designs.

• Analyze and optimize high-current delivery paths for AI/HPC workloads based on Powerlattice chiplets.

• Define and optimize end-to-end PDN solutions across: Die, Package, Interposer and PCB/system

Required:

Primary Location: Chandler, AZ (preferred). Secondary location: Vancouver, WA. Hybrid 3 days a week onsite in the office

What You Bring

• 8+ years of experience in power integrity and/or signal integrity for high-performance SoCs.

• Exceptional proficiency in power integrity or signal integrity tool chain and simulation flow.

• Hands-on experience extracting, building, and validating SoC package electrical models.

• Strong experience with package-level PI/SI, including substrates, interposers, and advanced packaging (2.5D / 3D).

• Deep proficiency with PI/SI simulation tools and analysis workflows.

• Strong debugging skills across simulation and electrical testing environments.

• High level of professionalism, discretion, and technical judgment.

• Comfortable working independently and proactively solving problems.

• Working experience at major processor or ASIC companies in the related technical area.

• Proven experience as engineering or project lead in a related technical area.

• Hands-on experience with electrical test methodologies and instrumentation for power integrity or signal integrity.

Compensation & Benefits