Semiconductor Test Engineer

Fractile is building silicon, systems and software which will redefine the frontier of AI: running the world’s most advanced models at radically higher speed and lower cost. We have an exceptional team across hardware and software capable of bringing about this change, and we are growing fast to meet demand and deliver our product at scale.

Summary

We are seeking an experienced Semiconductor Test Engineer to lead the development and deployment of manufacturing test solutions for next-generation AI accelerator devices. This role spans the full silicon lifecycle from first silicon bring-up through high-volume production, with responsibility for defining test strategy, developing ATE test content, debugging complex silicon issues, and optimizing yield, coverage, and test cost. The ideal candidate will bring deep expertise in DFT methodologies, high-speed interface testing, and advanced CMOS manufacturing, and will work closely with design, DFT, packaging, and manufacturing partners to ensure robust, scalable production of high-performance compute silicon.

Key Responsibilities

• Develop and maintain ATE test programs for an AI accelerator chip targeting high-volume manufacturing.
• Implement manufacturing test content for advanced CMOS designs including high-speed logic, SRAM, DRAM, and high speed IO blocks.
• Develop and debug structural and functional test content such as scan/ATPG, LBIST, MBIST, JTAG, and HSIO tests.
• Bring up first silicon on ATE, including pattern debug, tester correlation, shmooing, and corner analysis.
• Support testing of high-speed interfaces such as PCIe Gen6 and multi-GHz LPDDR, including at-speed tests and margining features.
• Execute silicon characterization and failure analysis to identify yield limiters and defect mechanisms.
• Optimize test coverage, test time, and cost while maintaining manufacturing robustness.
• Work with DFT and design teams to improve testability and close coverage gaps.
• Collaborate with OSATs and external partners on test program execution and debug.
• Support advanced packaging test flows, including die-to-die interconnect testing and package-level thermal considerations.
• Contribute to documentation of test programs, debug procedures, and manufacturing release materials. •
• Support qualification, reliability testing, and high-volume manufacturing ramp.

Required Qualifications

• 5+ years of hands-on semiconductor test engineering experience.
• Strong experience developing ATE test programs (Advantest 93K, Teradyne, or equivalent).
• Solid understanding of DFT methodologies (scan, ATPG, MBIST, LBIST) and memory test techniques.
• Experience debugging silicon issues at the tester and correlating failures to design or process causes.
• Familiarity with advanced CMOS nodes and production test challenges.
• Ability to work effectively in a cross-functional engineering environment.

Preferred Qualifications

• Experience testing AI accelerators, GPUs, networking ASICs, or other high-performance compute ICs.
• Experience with PCIe Gen5/Gen6, LPDDR4/5/6, or other high-speed interfaces.
• Exposure to advanced packaging, chiplets, or multi-die test flows.
• Experience improving yield, reducing test time, or optimizing cost in high-volume manufacturing.

How we work

• Ownership and execution: you will have full agency to drive your work forward
• Rapid iteration: we all work directly with top leadership to move from idea to hardware on ambitious timelines
• Full-stack engagement: hardware, software, silicon, and modelling teams all work closely together to create a product with generational impact
• Optimistic and pragmatic: we possess the will to win, and to do the hard work to get us there
• Team player mentality: the mission is bigger than any of us, and we have the curiosity and technical focus to see the best idea shipped, no matter who’s it is

About us

• Founded in 2022, team of 70+ which is expanding rapidly
• Modern, open offices in London and Bristol
• Collaborative, problem-solving culture built on deep curiosity, entrepreneurial initiative and technical fluency