Senior CPU RTL Design Engineer

Minimum qualifications:

• Bachelor's degree in electrical engineering, computer engineering, computer science, a related field, or equivalent practical experience.
• 8 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
• Experience with silicon validation and hardware debugging for phone/mobile-class application processors.
• Experience with logic techniques and RTL static checks (e.g., Lint and CDC).

Preferred qualifications:

• Master's degree or PhD in electrical engineering, computer engineering or computer science, with an emphasis on computer architecture.
• Experience with ARM architecture around debug features.
• Experience with the advanced microcontroller bus architecture (AMBA) protocol and system-level coherency management.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

• Contribute to CPU subsystem design, focusing on SoC integration related activities, functional debug and preparation for post-silicon testing.
  
• Participate in post-silicon CPU subsystem design activities for mobile devices, focusing on hardware-software integration and validation of CPU features in real silicon.
  
• Contribute to CPU subsystem micro-architecture and RTL design, delivering production-quality designs that meet power, performance, and area (PPA) goals for next-generation processors.
• Develop knowledge in CPU or AI accelerator architecture, design, and debug.
  
• Propose and implement performance-enhancing micro-architecture features, working with architects and performance teams to facilitate decision-making.