Staff Physical Design Engineer (R&D Engineering)

General Information

Job Title Staff Physical Design Engineer (R&D Engineering) Job ID 13411 Country India City Bengaluru Date Posted 13-Nov-2025 Job Category Engineering Job Subcategory R&D Engineering Hire Type Employee Remote Eligible No

Descriptions & Requirements

Job Description and Requirements

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a passionate engineering professional who thrives in collaborative, innovative environments. With a solid foundation in electrical engineering and extensive experience in backend physical design, you are driven by the challenge of delivering advanced semiconductor solutions. You bring expertise in RTL2GDS flows, physical implementation, and signoff methodologies, and you are eager to work on cutting-edge process nodes such as 16nm, 7nm, 5nm, and 3nm. Automation and process optimization are second nature to you, and you take pride in developing custom scripts to enhance design flows.

Your attention to detail is matched by your ability to see the bigger picture, ensuring designs meet stringent timing, power, and reliability targets. You are motivated by working across global teams and mentoring junior engineers, sharing your knowledge while learning from others. Communication comes naturally to you, whether collaborating internally or engaging with customers. Inclusion, diversity, and respect are values you champion, creating a welcoming environment for all. If you are excited to help shape the future of intelligent hardware and analytics, and ready to tackle complex challenges with creativity and determination, you will feel right at home in our team.

What You’Ll Be Doing:

• Leading backend implementation for SLM Controllers, Monitors, and Infrastructure IPs at advanced technology nodes (16nm to 3nm and beyond).
• Driving RTL2GDS physical design flows, including synthesis, partitioning, clock tree synthesis (CTS), place and route (P&R), static timing analysis (STA), and signoff.
• Developing and optimizing scripts and automation methodologies to improve design flow efficiency and quality.
• Collaborating closely with frontend designers, verification teams, and customers to ensure seamless integration and successful tapeouts.
• Mentoring junior engineers and supporting knowledge sharing within the team.
• Interfacing with internal and external stakeholders, providing technical guidance and solutions to meet project objectives.
• Contributing to the development and implementation of mixed-signal and soft IPs, ensuring robust design and signoff.

The Impact You Will Have:

• Enable rapid integration and deployment of next-generation SLM IPs, accelerating time-to-market for differentiated semiconductor products.
• Drive improvements in performance, power efficiency, area optimization, and reliability across multiple products.
• Contribute to the industry’s first end-to-end hardware IP, test, and analytics solutions, setting new standards in lifecycle management.
• Reduce risk for customers by ensuring robust design implementation and thorough signoff at advanced nodes
• Support the expansion of Synopsys’ SLM portfolio, helping customers achieve superior yield and schedule outcomes.
• Foster a culture of innovation, collaboration, and continuous learning within the team and broader organization.

What You’Ll Need:

• BS or MS degree in Electrical Engineering or related field, with 8+ years of relevant industry experience.
• Proven expertise in ASIC backend implementation, physical design, and signoff flows.
• Hands-on experience with industry-standard tools for synthesis, partitioning, CTS, P&R, STA (e.g., PrimeTime, ICC2, Design Compiler, Fusion Compiler)
• Strong scripting skills in TCL/PERL for flow automation and custom tool development.
• Deep understanding of high-frequency/multi-voltage designs, low-power methodologies, and layout closure techniques.  
• Experience with timing constraints, OCV/POCV, derates, crosstalk analysis, and design margin optimization.

Who You Are:

• An innovative problem solver with a forward-looking, automation-focused mindset.
• An effective communicator, able to collaborate in diverse, global teams and mentor others.
• Detail-oriented, with strong project execution and planning skills.
• Adaptable and open to new ideas, technologies, and methodologies.
• Committed to fostering an inclusive and respectful workplace.

The Team You’Ll Be A Part Of:

You will join the rapidly expanding Hardware-Analytics and Test (HAT) business unit, specifically within the SLM Hardware Group (SHG). Our team is dedicated to developing industry-leading SLM IPs and subsystems, combining deep technical expertise with a collaborative, innovative culture. We work across global teams to deliver solutions that meet the most demanding semiconductor lifecycle challenges, supporting customers in achieving their business goals.

Rewards And Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.