company logo

Design Verification Engineer

Meta.com

114k - 166k USD/year

Office

Sunnyvale, CA | Redmond, WA | Austin, TX

Full Time

Reality Labs focuses on delivering Meta's vision through AI-first devices that leverage our wearable technologies. The compute performance and power efficiency requirements require custom silicon. We are driving the state-of-the-art forward with highly integrated SoCs that leverage breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips will enable Meta’s Wearable devices that blend our real and virtual worlds throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistors, through architecture, firmware, and algorithms.Design Verification Engineer Responsibilities

Define and implement verification plans, and build test benches for block, IP, sub-system, and SoC level verification

Develop functional tests based on verification test plan

Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage

Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality

Debug, root-cause and resolve functional failures in the design, partnering with the Design team

Currently has, or is in the process of obtaining a Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta

2+ years of hands-on experience in SystemVerilog/UVM methodology or C/C++ based verification

2+ years experience in block/IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies

Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments

Experience with revision control systems like Mercurial(Hg), Git or SVN

Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle

Experience in development of Universal Verification Methodology (UVM) based verification environments from scratch

Experience verifying ARM/RISC-V based sub-systems and SoCs

Experience verifying CPU/GPU designs

Experience in one or more of the following areas: SystemVerilog Assertions (SVA), Formal, and Emulation

Track record of 'first-pass success' in Application-Specific Integrated Circuit (ASIC) development cycle

Minimum QualificationsPreferred Qualifications For those who live in or expect to work from California if hired for this position, please click here for additional information. About Meta Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics.
$114,000/year to $166,000/year + bonus + equity + benefits

Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.

Equal Employment Opportunity Meta is proud to be an Equal Employment Opportunity employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, reproductive health decisions, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, political views or activity, or other applicable legally protected characteristics. You may view our Equal Employment Opportunity notice here. Meta is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures. If you need assistance or an accommodation due to a disability, fill out the Accommodations request form.

Design Verification Engineer

Office

Sunnyvale, CA | Redmond, WA | Austin, TX

Full Time

114k - 166k USD/year

November 8, 2025

Meta.com

Meta