Senior Engineer II-Validation

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Job Description:

The project involves validating all the features and interfaces supported on the G6 FPGA by creating and using validation designs that are partitioned into RTL and Embedded Processor Application. Test and debug the silicon on board with the help of lab equipment and protocol testers. G6 validation performed by Consultant team will include the following activities:

• Validation design creation using Microchip’s FPGA design flow
• RTL and Embedded C based test design development
• Validation of all features of G6
• Debug and root cause analysis, validating workaround and fixes

The scope of the consultant team is to validate with the requirements:

• Work location will be Microchip Hyderabad office and will involve working in the lab
• Study of specification and validation plans
• Develop validation designs, testbenches and verify in simulation using the simulation models.
• Board schematic verification
• Create and maintain required hardware setup, bring up the silicon and validate use cases capture results
• Debug the design to rule out finger trouble issue, work with cross functional team to perform experiments to root cause the issue
• Documentation of test results, reviewing with stakeholder and getting sign-off
• Providing regular detailed status reports, presenting status in dept meetings, follow through on action items. Attend deep dive and debug discussions with teams in the US.
• Develop automation and regression design
• File Bugzilla/jira tickets during the design creation and validation phase, perform the experiments required to isolate and root cause, validate workaround/fixes and ensure closure during sign-off  
• Review the intermediate and final deliverables as per the agreed plan

Requirements/Qualifications:

• Strong hands-on FPGA Silicon validation experience
• Strong hands-on validation experience in one or many of the below protocols
• PCIe Gen4/5
• DDR 4/5
• 100G/50G/40G/25G/10G Ethernet
• USB 3.2
• JESD204C
• 1588 PTP
• MIPI
• MACSEC
• Hands-on systems level design and debug experience with the following high-speed memory interfaces:
• DDR4/LPDDR4/DDR5/LPDDR5 memories
• QDR II+/ QDR IV memories
• Good knowledge of embedded processors and peripherals such as SPI, I3C, UART, NOC, Trace and USB     
• Responsible for developing testbenches and verifying validation designs
• Responsible for handling complex use cases on above protocols at block level and subsystem level
• Strong hands-on experience in ‘C’ programming language experience
• Validating FPGA configuration and security features
• PCIe Gen4/5
• DDR 4/5
• 100G/50G/40G/25G/10G Ethernet
• USB 3.2
• JESD204C
• 1588 PTP
• MIPI
• MACSEC
• DDR4/LPDDR4/DDR5/LPDDR5 memories
• QDR II+/ QDR IV memories

Travel Time:

No Travel

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