Senior PCIe Silicon Validation Engineer, Google Cloud

Minimum Qualifications:

• Bachelor's degree in Electronic Engineering or Computer Engineering, or equivalent practical experience.
• 5 years of experience in Peripheral Component Interconnect Express (PCIe) validation and testing (e.g., compliance, system level debug).
• Experience in embedded C/C++ code development.

Preferred Qualifications:

• Experience in PCIe compliance measurements using high-end equipment (e.g., Analyzer, Exerciser).
• Experience with development using pre-silicon tools (e.g., Field Programmable Gate Array (FPGA)/Emulator).
• Experience in lab equipment for PCIe testing (physical or protocol level).
• Knowledge of Peripheral Component Interconnect Express (PCIe) domain.
• Knowledge of ARM based SoC architecture (e.g., Boot flow, High-speed I/F initialization).

About The Job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

Responsibilities

• Take overall ownership of the PCIe subsystem silicon validation, including PCIe physical electrical testing, timing measurements and enhancements.
• Work with Silicon Validation, Firmware and Platform teams on requirements, test definition, implementation and execution.
• Support product ramp, integration of PCIe peripherals, and debug of PCIe related failures.
• Work with teams on test definition, timing budget analysis and provide system level breakdown of timing budget (e.g., standalone, full system load).
• Support platform ramp in debugging, integration of new Peripheral Component Interconnect Express (PCIe) endpoints, and triage for PCIe related failures.