Senior Design Verification Engineer, Networking, Google Cloud

Minimum Qualifications:

• Bachelor's degree in Electrical Engineering or equivalent practical experience.
• 8 years of experience verifying digital logic at Register-Transfer Level (RTL) using SystemVerilog or Specman/E for Field Programmable Gate Arrays (FPGAs) or Application-specific integrated circuit (ASICs).
• Experience with Central Processing Unit (CPU ) implementation, assembly language, or compute System on a Chip (SOC).
• Experience verifying digital systems using standard IP components/interconnects (microprocessor cores, hierarchical memory subsystems).
• Experience creating and using verification components and environments in standard verification methodology.

Preferred Qualifications:

• Master’s degree in Electrical Engineering or Computer Science.
• Experience with UVM, SystemVerilog, or other scripting languages (e.g., Python, Perl, Shell, Bash, etc.).

About The Job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As an Executive CPU Design Verification Engineer, you will be a part of Research and Development team to verify digital designs, develop constrained-randomn test environments and drive system testing to closure. You will collaborate with design and verification teams, manage the verification life-cycle and uncover bugs through rigorous corner-case testing.

The AI and Infrastructure team works on the world’s toughest problems, redefining what’s possible and the possible easy. We empower Google customers by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Googler Cloud customers, and billions of Google users worldwide. We’re at the center of amazing work at Google by being the “flywheel” that enables our advanced AI models, delivers computing power across global services, and offers platforms that developers use to build services.

In AI and Infrastructure, we shape the future of hyperscale computing by inventing and creating world-leading future technology, and drive global impact by contributing to Google infrastructure, from software to hardware (including building Vertex AI for Google Cloud). We work on complex technologies at a global scale with key players in the AI and systems space. Join a team of talented individuals who not only work together to keep data centers operating efficiently but also create a legacy of driving innovation by building some of the most complex systems technologies.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Responsibilities

• Plan and execute the verification of digital design blocks by understanding specifications and working with design engineers to define key verification scenarios.
• Develop and refine random verification environments using SystemVerilog/UVM or Specman to ensure effective test coverage.
• Define and implement various coverage measures to capture stimulus and corner-case scenarios.
• Collaborate with design engineers to debug tests and ensure functional correctness of design blocks.
• Drive coverage analysis to identify verification gaps and demonstrate progress towards tape-out.