Junior Design Verification Engineer, Networking, Google Cloud

Minimum Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 1 year of experience creating and using verification components and environments in standard verification methodology.
• Experience verifying digital logic at Register Transfer Level (RTL) level using SystemVerilog or Specman/E for Field Programmable Gate Arrays or ASICs.

Preferred Qualifications:

• Master’s degree in Electrical Engineering, Computer Science, or a related field.
• Experience with Universal Verification Methodology (UVM), SystemVerilog, or other scripting languages (e.g., Python, Perl, Shell, Bash, etc.).
• Experience with CPU implementation, assembly language or compute SOCs.

Experience verifying digital logic at Register Transfer Level (RTL) level using SystemVerilog or Specman/E for Field Programmable Gate Arrays or ASICs.

About The Job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a Design Verification Engineer, you will work as part of a Research and Development team building verification components, constrained-random testing, system testing, and verification closure. As part of our server chip design team, you will verify digital designs. You will collaborate with design and verification engineers in active projects and perform verification. You will be responsible for the full life-cycle of verification which can range from verification planning, test execution or collecting and closing coverage.

The AI and Infrastructure team works on the world’s toughest problems, redefining what’s possible and the possible easy. We empower Google customers by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Googler Cloud customers, and billions of Google users worldwide. We’re at the center of amazing work at Google by being the “flywheel” that enables our advanced AI models, delivers computing power across global services, and offers platforms that developers use to build services.

In AI and Infrastructure, we shape the future of hyperscale computing by inventing and creating world-leading future technology, and drive global impact by contributing to Google infrastructure, from software to hardware (including building Vertex AI for Google Cloud). We work on complex technologies at a global scale with key players in the AI and systems space. Join a team of talented individuals who not only work together to keep data centers operating efficiently but also create a legacy of driving innovation by building some of the most complex systems technologies.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Responsibilities

• Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
• Create and enhance constrained-random verification environments using SystemVerilog or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools.
• Identify and write all types of coverage measures for stimulus and corner-cases.
• Debug tests with design engineers to deliver functionally correct design blocks.
• Apply close coverage measures to identify verification holes and to show progress towards tape-out.