Digital designer for ultra-low power MLP (Internship)

The Role:

The candidate will design an ultra-low power MLP hardware accelerator for image inference in Verilog. He/She will evaluate PPA parameters and benchmark the design with similar architecture from literature. Building on Openchip’s existing MLP design, the candidate will have the chance to contribute innovative ideas to further optimize performances and power consumption.

Expected duration: 3 to 5 months. It is an internship role.

Key Responsibilities:

• Simulate OpenChip’s ultra-low power MLP architecture in Python
• Implement the defined MLP architecture in Verilog
• Run Verilog simulations and evaluate PPA metrics
• Optimize the architecture for improved performance

Key Qualifications:

• Basic understanding of MLP architectures for image inference
• Knowledge of microelectronics and digital design
• Good Verilog programming skills
• Basic experience with Python

Preferred Qualifications:

• Familiar with PyTorch and TensorFlow frameworks
• Understanding of hardware implementation and synthesis processes

Soft Skills:

• Good communication and presentation capabilities

• Proactive And Solutions-Oriented.

• Highly organized and process-driven.
• Strong interpersonal skills; ability to handle sensitive situations with empathy and clarity.
• Team player who thrives in a dynamic and fast-paced environment.

We are looking for outstanding people willing to join our mission to change the silicon industry and help build a better world. If you feel identified with Openchip, please contact us.

At Openchip & Software Technologies S.L., we believe a diverse and inclusive team is the key to groundbreaking ideas. We foster a work environment where everyone feels valued, respected, and empowered to reach their full potential—regardless of race, gender, ethnicity, sexual orientation, or gender identity.