Principal RFIC Top-level Design Engineer

Bridgecom.com

Office

Linz, Austria

Full Time

As a Principal RFIC Top-level Design Engineer at Bridgecom, you will lead the delivery of top-level RFIC designs by integrating key sub-components such as the receive and transmit chains. You will define and optimize the chip floorplan, supply and ESD architecture, and packaging concept to ensure robust performance, manufacturability, and compliance with industry standards.

Own the RFIC top-level design and layout, managing interfaces with concept, layout, verification, PCB design, test, packaging, and foundry teams.
Define the ball-out and chip floorplan in collaboration with subsystem leads to optimize area, routing efficiency, and minimize crosstalk from project start onwards.
Lead the ESD concept and testing strategy; sign off using ESD event simulations and expert reviews.
Architect the top-level supply concept, balancing performance requirements with implementation efficiency.
Drive tape-out readiness in partnership with the top-level layout team through detailed work package planning and progress tracking.
Execute tape-out, including technology flavor selection, foundry DRC compliance, and waiver management.
Decompose complex EM simulation scenarios into feasible tasks, interpret results, and guide resolution.
Serve as the technical interface to foundry and OSAT; conduct top-level design and layout reviews to ensure quality and manufacturability.
Support post-silicon debug and bring-up activities as needed.
Proven experience in product development from concept through ramp-up.
Strong communication and collaboration skills; able to lead and contribute effectively in cross-functional teams.
Skilled in structuring complex problems into executable work packages; proficient in structured problem solving.
Able to maintain and communicate a clear technical narrative (“red thread”) across complex topics.
Hands-on design and layout experience in advanced CMOS or SOI technologies; FinFET node experience is a strong plus.
Broad knowledge across analog, digital, mixed-signal, and RF design, with deep expertise in at least one domain.
Experience with mobile communication standards and 3GPP is highly desirable.
Deep understanding of analog-on-top and digital-on-top design flows, including integration of external IP deliveries.
Demonstrated ability to manage uncertainty through early feasibility and area studies.
In-depth knowledge of package technologies, including SiP; able to evaluate trade-offs and limitations.
Proficient in automating design tasks using Python and/or SKILL.
Solid understanding of ESD models (HBM, CDM) and protection strategies.
Familiarity with failure analysis tools and techniques; able to select appropriate methods for issue resolution.
Tool proficiency: Cadence® Virtuoso®, Keysight® SoS, EM simulators (EMX®, HFSS®), Python™, SKILL®.
Master’s degree in Electrical Engineering or a related field; Ph.D. is a plus.
Preferably 10-15 years of work experience in the RFIC design environment.
The opportunity to work on next-generation 5G RF semiconductor technologies tailored IoT and automotive markets.
A dynamic environment where engineers get the full picture of a product development cycle, not just execute isolated tasks.
An inclusive and diverse team in a thriving tech startup setting.
Individual growth opportunities in a growth company.
Continuous learning through collaboration with senior engineers and hands-on exposure across multiple areas of semiconductor development.

We are looking forward to receiving your application including your CV and a Cover Letter!