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Staff Engineer, RTL Design, Chiplet

Tenstorrent.com

100k - 500k TWD/year

Office

新北市, New Taipei City, Taiwan

Full Time

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

Tenstorrent is leading the industry on cutting-edge AI and CPU technology, redefining performance expectations, scalability, and efficiency. Our diverse team of technologists has developed high-performance compute architectures from the ground up, with a passion for solving the hardest problems in compute. We are growing our hardware team and are seeking an experienced Microarchitecture & RTL Engineer to join us.

In this role, you will work on the implementation of digital IPs for Tenstorrent’s CPU and AI/ML accelerator chiplets, collaborating with cross-functional teams to deliver robust and scalable designs.

This role is remote, based out of Taiwan 

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Responsibilities:

  • RTL design and Microarchitecture of a system management, security sub-systems, fabric, and SoC integration. 
  • RTL coding in Verilog leveraging both industry tools as well as open-source infrastructure
  • Work with design, test and post silicon validation teams for high quality delivery of the security subsystem
  • Evaluate and integrate 3rd party IP components in the design
  • Drive trade-offs for your logic by working closely with architecture, DV and physical design engineers to craft optimal solutions that meet the design goals
  • Deploy innovative techniques for improving power, performance and area of the design, drive experiments with RTL and evaluate synthesis, timing and power results
  • Debug RTL/logic issues across various hierarchies (core, chip) in both pre-silicon and post-silicon environment
  • Enhance RTL design environment, tools and infrastructure

Experience & Qualifications:

  • BS/MS/PhD in EE/ECE/CE/CS with at least 5 years of experience
  • Knowledge of industry standard protocols such as AXI, AHB, APB
  • Expertise in logic design and ability to evaluate functional, performance, timing and power for you design
  • Strong experience with hardware description languages (Verilog, VHDL), simulators (VCS, NC, Verilator), Synthesis and Power tools
  • Expertise in microarchitecture definition and specification development
  • Strong problem solving and debug skills across various levels of design hierarchies

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology.  Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2).   These requirements apply to persons located in the U.S. and all countries outside the U.S.  As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency.  If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

Staff Engineer, RTL Design, Chiplet

Office

新北市, New Taipei City, Taiwan

Full Time

100k - 500k TWD/year

October 1, 2025

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Tenstorrent

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