Associate Engineer, Physical Design

ASIC/Layout Design Engineer 1

• Position Summary: The ASIC/Layout Design Engineer 1 position is responsible for performing basic physical design and layout activities within
• our semiconductor company. This position supports ASIC layout development, assists with physical verification, and helps implement design components.
• The role requires fundamental understanding of semiconductor layout principles, technical skills, and attention to detail to support the development of
• integrated circuit physical designs in the complex semiconductor environment.
• Key Responsibilities:
• Layout Design Support (30%): • Support physical layout of standard cells, memory blocks, and basic circuit elements • Assist with implementation
• of layout designs based on schematics and specifications • Help with placement and routing of components and interconnects • Support floorplanning and
• power distribution network development • Maintain layout documentation and design files
• Physical Verification Support (25%): • Assist with design rule checking (DRC) and layout vs. schematic (LVS) verification • Support resolution
• of basic physical verification issues • Help with design rule violations identification and correction • Participate in verification run setup and execution
• • Document verification results and issue resolutions
• Layout Data Preparation (15%): • Support preparation of layout data for manufacturing • Assist with design for manufacturing (DFM) checks and
• optimizations • Help with mask data preparation and file generation • Support tape-out activities and data transfer • Maintain design databases and
• version control
• Design Tool Support (10%): • Support physical design tools and EDA environments • Assist with design kit implementation and updates • Help maintain
• layout libraries and technology files • Support design flow execution and automation • Assist with tool setup and configuration
• Technology Migration Support (10%): • Assist with layout migration between technology nodes • Support porting of designs to new process technologies
• • Help implement technology-specific design rules and constraints • Participate in migration verification and validation • Document process differences and
• layout adjustments
• Technical Learning and Development (10%): • Develop understanding of physical design principles and methodologies • Learn semiconductor manufacturing
• processes and design rules • Support implementation of layout best practices • Participate in technical training and development activities • Increase
• knowledge of semiconductor technologies and physical design approaches
• Education and Experience:
• • Bachelor's degree in Electrical Engineering, Computer Engineering, or related technical field • 0-2 years of experience in ASIC layout, physical design,
• or related role • Basic knowledge of semiconductor design and layout principles • Experience with EDA tools and design environments • Familiarity with IC
• layout verification preferred