Silicon Design Verification Engineer III

Minimum Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 4 years of experience with SystemVerilog, Design Verification Test, Universal Verification Methodology.
• 3 years of experience working with test methodologies, creating test plans, and writing test cases.

Preferred Qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience in low-power design verification.

About The Job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a part of the Google Silicon Platforms team, you will work on the verification of the backbone of Google’s SOC offerings. You will collaborate with hardware architects and design engineers for functional and performance verification of the infrastructure IP, interconnects, caches, memory management and system services. You will also work on developing high performance VIPs for protocols supported by our SOCs, and closely collaborate in the deployment of the verification stack across a heterogeneous set of IPs. You will include build and verify a generalized system topology abstractions, and develop the associated methodologies and tools needed to solve the problem.The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.

Responsibilities

• Plan the verification of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
• Create and enhance constrained-random verification environments using System Verilog and UVM.
• Identify and write all types of coverage measures for stimulus and corner-cases.
• Debug tests with Design Engineers to deliver functionally correct design blocks.
• Close coverage measures to identify verification holes and to show progress towards tape-out.