Full Chip CAD Physical Design Engineer

Minimum Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Science, or a related field, or equivalent practical experience.
• 4 years of experience in Electronic Design Automation (EDA) tools and RTL2GDS flows.
• Experience in the semiconductor/EDA industry.

Preferred Qualifications:

• Master’s degree in Computer Engineering/Electronics Engineering, or a related field.
• Experience with silicon quality or reliability.

About The Job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Responsibilities

• Demonstrate an understanding of the Register-Transfer Level (RTL) to Graphic Data Stream (GDS) II flow.
• Manage the implementation of large, complex system-on-chips (SoCs), subsystems, and sub-wrappers, and demonstrate an understanding of associated issues and solutions.
• Utilize floorplanning, power grid design, and place-and-route methodologies. Use synopsys tools like Floorplan Compiler (FC) and formality.
• Exhibit an understanding of advanced node design (e.g., 5nm and below) and related optimization techniques.
• Script in Synopsys TCL, and Python.