Stage/Internship - Development of an FPGA based AXI4 lite interface to multiple UART IP

John Cockerill, enablers of opportunities

Driven since 1817 by the entrepreneurial spirit and thirst for innovation of its founder, the John Cockerill Group develops large-scale technological solutions to meet the needs of its time: facilitating access to low carbon energies, enabling sustainable industrial production, preserving natural resources, contributing to greener mobility, enhancing security and installing essential infrastructures. 

Its offer to businesses, governments and communities consists of services and associated equipment for the sectors of energy, defence, industry, the environment, transports, and infrastructures. With more than 8,000 employees, John Cockerill achieved a turnover of € 1.417 billion in 2024 in 28 countries, on 5 continents. 

John Cockerill has been providing its expertise to the defense industry for 200 years. Today, John Cockerill Defense offers Cockerill® modular gun turrets from 25 to 120 mm caliber, Arquus® high-mobility vehicles, technical and tactical training on these systems, and Agueris simulators.

Your Mission:

The goal of this internship is to develop a proof-of-concept of an IP which interfaces multiple UARTs through a single AXI4 lite register interface. The IP must be integrated into a Xilinx FPGA technology (e.g. zynq ultrascale+). The IP should interface up to 8 UART interface at the same time.The UART must have configurable baudrate. The register map interface should be designed in a efficient way so that data can be pushed or retrieved fastly .The proof-of-concept shall be developed on a Xilinx development board.

1. Define the needs

You will start by understanding the UART protocol, then the architecture and the integration of IPs in a Xilinx FPGA.

2. Conceptual Design

You will do some research on existing IP.

You will define and evaluate the development boards and FPGA needs.

3. Design and test of single UART interface IP

You will create an AXI4 lite with a single UART IP. The IP can be coded from scratch or based on existing IPs. You will then validate the behavior of the IP using simulation testing tools (VHDL and/or UVM testbench) .

4. Scale up the IP

You will modify the IP and add several UART interface (up to 8). You will then check the behavior of the IP on simulation.

5. Software programming and HW tests

You will test the IP integrated in a small software project in real conditions on hardware. You must develop the software and access the stability and the performances of the design.

Subject Discussed:

UART, AXI4-Lite
C Software programmation
Xilinx FPGA
Vivado development tools
VHDL
Simulation testbench 

Your Profile:

• Student in a master's degree education level in electronic
• Minimum level B2 in French and English
• Available for at least of 2-3 months

Your Internal Support:

During this internship, you will be supported by the electronic R&D department and the electronic industrialization and prototyping department of John Cockerill Defense. The internal supervisors will be:

• Matthieu Close (R&D engineer) – project definition
• Maxime Javaux (R&D engineer) – project definition
• Quentin Gaspart (R&D engineer) – FPGA design 

What We Offer You:

• Immersion in a stimulating, technology-driven environment
• Concrete and rewarding responsibilities
• A caring and passionate team

We look forward to receiving your application and meeting you.

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