ASIC Engineer, Networking Architecture and Modeling
Meta.com
142k - 203k USD/year
Office
Sunnyvale, CA | Menlo Park, CA
Full Time
As a Networking ASIC Engineer on the Infrastructure Silicon team at Meta, you will play a key role in shaping the networking architecture for leading-edge AI training and inference accelerators. You will work closely with other architecture engineers to define networking architecture specifications and then develop high-fidelity C++ models—including QEMU, NIC, RoCE, and UAL (Ultra Accelerator Link) models—to enable early software development, architecture exploration, and performance analysis.
You will collaborate with cross-functional teams working on data center networking architecture, network system design, micro-architecture, RTL design, Design Verification, Firmware/Software development, Pre-Post silicon validation, and Program Management to deliver first-pass functional silicon.ASIC Engineer, Networking Architecture and Modeling Responsibilities
$142,000/year to $203,000/year + bonus + equity + benefits
Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.
Equal Employment Opportunity Meta is proud to be an Equal Employment Opportunity employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, reproductive health decisions, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, political views or activity, or other applicable legally protected characteristics. You may view our Equal Employment Opportunity notice here. Meta is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures. If you need assistance or an accommodation due to a disability, fill out the Accommodations request form.
You will collaborate with cross-functional teams working on data center networking architecture, network system design, micro-architecture, RTL design, Design Verification, Firmware/Software development, Pre-Post silicon validation, and Program Management to deliver first-pass functional silicon.ASIC Engineer, Networking Architecture and Modeling Responsibilities
- Collaborate with architecture engineers to define specifications for one or more subsystems of an integrated or discrete NIC ASIC
- Develop and maintain C++ models of networking subsystems—including QEMU, NIC, RoCE, and UAL models—for architecture exploration, performance analysis, and software development
- Provide technical support in functional model development to enable networking firmware creation
- Support networking model development, performance analysis, and correlation with design implementation
- Work with software and firmware teams to ensure C++ models are aligned with system requirements and enable early software bring-up
- Provide expected key performance indicators for performance analysis of the subsystems
- Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
- 6+ years of experience working in networking ASIC development targeted for enterprise, data-center, or hyperscaler use cases
- Hands-on experience developing and maintaining C++ models for NIC, RoCE, UAL or similar networking architectures
- Experience with QEMU or similar simulation frameworks for hardware modeling
- Experience working with large clusters of Ethernet or RoCEv2 or Infiniband or NVlink fabrics
- Knowledge of ASIC development on advanced process nodes using chiplet-based solutions
- Experience and knowledge of data center networking solutions used in large-scale clusters, including shallow buffered switches, TOR switches, routers, GPU and CPU servers/acceleration devices
- Experience in using performance models, performance analysis, and performance correlation
- Experience in developing PCIe-based NICs, Front-end and Back-end NICs
- Experience with QEMU NIC modeling, UAL modeling, and RoCE modeling using C++
- Experience integrating C++ models with system simulation environments (e.g., QEMU, SystemC, or custom frameworks)
$142,000/year to $203,000/year + bonus + equity + benefits
Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.
Equal Employment Opportunity Meta is proud to be an Equal Employment Opportunity employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, reproductive health decisions, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, political views or activity, or other applicable legally protected characteristics. You may view our Equal Employment Opportunity notice here. Meta is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures. If you need assistance or an accommodation due to a disability, fill out the Accommodations request form.
ASIC Engineer, Networking Architecture and Modeling
Office
Sunnyvale, CA | Menlo Park, CA
Full Time
142k - 203k USD/year
September 24, 2025