Senior Physical Design Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission.

As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Microsoft’s Compute Silicon & Manufacturing Engineering team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for seasoned engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.

We are looking for a Senior Physical Design Engineer to join the team.

Responsibilities

• Lead and manage floorplanning and design planning activities to optimize timing-critical and large sub-chips for power, performance, and area (PPA).
• Drive end-to-end execution from synthesis through place-and-route for large sub-chips and/or full-chip designs, ensuring completion of all signoff stages including timing, physical verification, EMIR, formal equivalence, and low-power verification.
• Coordinate effectively across cross-functional teams such as DFT, RTL/Design/IP, STA, CAD, Architecture, Power & Performance, and both internal and external stakeholders.
• Influence design tools, flows, and methodologies in construction, signoff, and optimization through a data-driven approach.
• Develop and implement robust clock distribution strategies that meet design specifications.
• Make sound technical trade-offs between power, area, and timing to achieve optimal design outcomes.
• Provide technical leadership and foster collaboration across teams to deliver the best possible solutions, aligned with a One Microsoft mindset.

Qualifications

Required Qualifications:

• Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience
• 4+ years experience in semiconductor design.
• 3+ years experience implementing designs through synthesis, floorplanning, place and route, extraction, timing, and physical verification.
• OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience
• OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience
• OR equivalent experience.

Other Requirements:

• Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter. 

Preferred Qualifications:

• Experience in large-scale SoC, CPU, and IP design tape-outs using advanced foundry process nodes.
• Cabable communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams.
• Proficient in power rollup methodologies with hands-on experience at both block and full-chip levels.
• Project management capabilities with a proven ability to manage multiple concurrent projects effectively.
• Expertise in constraints generation, static timing analysis (STA), timing optimization, and timing closure.
• Understanding of design trade-offs across power, performance, and area (PPA).
• Hands-on experience with clock tree synthesis (CTS) and global clock distribution in complex multi-voltage, multi-clock, multi-domain, and low-power designs.
• Experienced in industry-standard EDA tools including PrimeTime, StarRC, Design Compiler, ICC, and Innovus.
• Advanced proficiency in Engineering Change Order (ECO) implementation for power and timing convergence, with solid knowledge of functional and DFT ECO closure methodologies.
• Effective collaboration with PD, DFT, STA flow, CAD teams, and EDA tool vendors to ensure seamless integration and execution.
• Demonstrated ownership of deliverables and cross-functional teamwork.
• Track record in mentoring, influencing teams, and driving alignment through clear and effective communication.
• Understanding of formal equivalence checks, low power (LP), Unified Power Format (UPF), reliability, signal integrity (SI), and noise analysis.
• Analytical and problem-solving skills, complemented by advanced scripting capabilities in Perl, TCL, and Python.

Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $158,400 - $258,000 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: US corporate pay information | Microsoft Careers

Microsoft will accept applications for the role until Sept 23 2025.

Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances.  We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request via the Accommodation request form.

Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.

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