Silicon Layout Engineer, Raxium

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, a related field, or equivalent practical experience.
• 8 years of experience in physical layout design and verification.
• Experience in industry-standard layout tools and methodologies.

Preferred qualifications:

• Experience with high-density layout techniques and mixed-signal design.
• Understanding of microLED display technology and its impact on layout considerations.
• Excellent problem-solving skills, communication and collaboration skills, with attention to detail.

About the job

As a Silicon Layout Engineer, you will be responsible for transforming circuit designs into physical layouts, ensuring optimal performance, reliability, and manufacturability. You will work closely with circuit designers to bring their outlooks to life.Google's Raxium display group has established a revolutionary semiconductor materials display technology that enables new functionality in display products, bringing to users a closer and more natural linkage between the digital and physical realms in applications such as augmented reality (AR) and light-field display. With start-up roots and a state-of-the-art compound semiconductor fab in Silicon Valley, Raxium is seeking to build upon its engineering team with an aim to disrupt next-generation display markets.
The US base salary range for this full-time position is $156,000-$229,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.
The US base salary range for this full-time position is $156,000-$229,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Collaborate with analog and digital circuit designers to understand design requirements and constraints.
• Execute full chip integration and support foundry submissions by developing Layout Versus Schematic, (LVS/DRC) extraction flow for full chip and analog modules.
• Create and verify physical layouts for microLED display driver circuits while performing parasitic extraction and analysis to ensure compliance with design rules, achieve performance goals and maintain signal integrity with minimize noise coupling.
• Work with foundry partners to address design rule checks (DRCs) and ensure successful tape-out.
• Improve layout methodologies and contribute to the team's technical expertise.