Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at www.asteralabs.com.

Job Description

We are looking for a Senior Design Verification Engineers with strong problem-solving skills and the ability to develop comprehensive verification methodologies for complex ASICs. Experience with SystemVerilog, C, C++, Python, or other scripting languages would be a plus. Using your coding and analytical skills, you will contribute to the functional verification of cutting-edge designs. You'll be responsible for the full lifecycle of verification, from planning to writing tests to debugging, collecting, and closing coverage. You'll also collaborate with software and system validation teams to develop test plans and execute them on emulation platforms.

Basic Qualifications

Strong academic and technical background in electrical engineering. At minimum, a Bachelor's in EE is required, and a Master's is preferred.
≥5 years' experience verifying and validating complex SoCs for Server, Storage, and Networking applications.
Knowledge of industry-standard simulators, revision control systems, and regression systems.
Professional attitude with the ability to prioritize a dynamic list of multiple tasks and work with minimal guidance and supervision.
Strong communication and collaboration skills with enthusiasm for tackling varied and complex technical challenges.
Authorized to work in the US and available to start immediately.

Required Experience

Experience with a full verification lifecycle based on SystemVerilog/UVM/C/C++.
Proven ability to implement and deploy mixed verification methodologies including both directed and constrained random approaches.
Experience with various debugging techniques and coverage analysis methods. Experience in formal verification methods is a plus.
Must be able to work independently to develop test plans and related test sequences to generate stimuli, and work collaboratively with RTL designers to debug failures.
Identify and implement all types of coverage measures for stimulus and corner cases. Close coverage gaps to identify verification holes for high-quality tape-out.

Preferred Experience

Experience with switching verification, including packet processing, forwarding engines, and network switching architectures.
Prior experience using Verification IPs from 3rd party vendors with one or more communication protocols such as PCI-Express, Ethernet, InfiniBand, DDR4/5, NVMe, USB, etc.
Experience with directed, constrained random and assertion-based verification methodologies, and formal methods.
Working experience with scripting tools (Perl/Python) to automate verification infrastructure.

The base salary range is USD 147,000 - USD 195,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.