Positron.ai specializes in developing custom hardware systems to accelerate AI inference. These inference systems offer significant performance and efficiency gains over traditional GPU-based systems, delivering advantages in both performance per dollar and performance per watt. Positron exists to create the world's best AI inference systems.

Hiring Requisition: Principal ASIC Design Engineer

Position: Principal ASIC Design Engineer

Company: Positron.ai

Job Type: Full-time

Reports To: Director of ASIC Engineering

Location: (Onsite/Hybrid/Remote—your preference)

Company Overview

Positron.ai specializes in developing custom hardware systems to accelerate AI inference. Our systems deliver step-function improvements in performance per dollar and performance per watt versus traditional GPU-centric approaches. We exist to create the world’s best AI inference systems.

Position Overview

As a Principal ASIC Design Engineer, you will provide technical leadership across the full ASIC design lifecycle—owning the architecture, microarchitecture, RTL implementation, and front-end signoff of major subsystems for Positron.ai’s inference ASICs/SoCs. You will drive architectural decisions, establish best-in-class design methodologies, and ensure that all silicon meets aggressive PPA, schedule, and quality targets. This role is both highly technical and strategic: you will shape silicon architecture, mentor engineering teams, and represent ASIC design in cross-functional and executive discussions.

Key Responsibilities

Architecture & Technical Leadership:

Define system-level architecture and guide microarchitecture decisions for complex subsystems and cross-chip fabrics.
Lead technical scoping, partitioning, and tradeoff analyses across performance, power, and area.

RTL Design & Signoff Ownership:

Deliver production-quality, parameterized SystemVerilog RTL for critical IP and subsystems with robust power/clock intent and embedded assertions.
Drive front-end signoff activities (lint, CDC/RDC, DFT, synthesis/STA) and ensure readiness for back-end implementation.

High-Performance Interface & Memory Integration:

Architect and integrate advanced interconnects (AXI/CHI/ACE), DMA engines, coherency protocols, and high-speed memory interfaces (HBM/DDR) to meet demanding throughput and latency targets.
Coordinate with IP vendors and internal teams for seamless system integration.

Methodology, Standards & Innovation:

Define and maintain ASIC design methodology, coding standards, and reusable IP collateral across the organization.
Lead automation efforts (Python/Tcl/Make/CI) to improve team efficiency and design quality.

Cross-Functional Influence:

Collaborate closely with Architecture, Verification, PD, and Software to align requirements and resolve design issues quickly.
Present technical recommendations to leadership and influence product-level decisions.

Mentorship & Team Development:

Mentor and coach ASIC engineers across experience levels.
Lead technical reviews, fostering a culture of engineering excellence and continuous improvement.

Required Qualifications

BS/MS in EE/CE (or related) with 12+ years of ASIC/SoC RTL design experience, including technical leadership of large-scale, high-performance silicon projects.
Proven success in delivering blocks and subsystems from spec → architecture → microarchitecture → RTL → silicon with exceptional PPA results.
Expert SystemVerilog RTL skills and deep knowledge of clocking, resets, CDC/RDC, and protocol correctness.
Extensive experience with front-end design flows, EDA tools, and industry best practices.
Hands-on expertise in at least four of: HBM/DDR, PCIe/CXL, AMBA AXI/ACE/CHI, large-scale cache/memory hierarchies, high-throughput datapaths, NoC design.
Strong track record of influencing architecture and methodology decisions at the chip or system level.

Preferred Qualifications

Leadership experience in AI/ML accelerator design (matrix/vector engines, compression, NoC bandwidth planning).
Deep formal verification/SVA expertise for property checking and assertion-based design.
Low-power design leadership, including clock-/power-gating strategies, multi-voltage/multi-domain flows, and UPF/CPF.
Proven ability to define and roll out new ASIC design methodologies across teams.
Familiarity with RISC-V subsystems, coherence protocols, or advanced customer-owned tooling (COT) flows.

Why Join Us?

Shape the architecture and execution of groundbreaking AI inference hardware with a high-caliber, collaborative team.
Influence both the technology direction and the engineering culture of a rapidly growing company.
Competitive salary + equity, comprehensive benefits, and a flexible work environment.
Opportunities to drive innovation at the intersection of architecture, design, and product strategy.

Interested?

Apply with your resume and a brief note describing a subsystem or architecture you led from concept to tape-out, highlighting the PPA, methodology, and strategic tradeoffs you drove.