ASIC Engineer, Design
Meta
212k - 291k USD/year
Office
Sunnyvale, CA | Austin, TX
Full Time
Meta is hiring ASIC Design Engineers within our Infrastructure organization to build cutting edge ASICs in fields such as machine learning, network acceleration and video transcoding. We are looking for individuals with demonstrated track record that spans one or more of the key areas required to build successful world-class complex SoC and IP for data center applications.ASIC Engineer, Design Responsibilities
US$212,000/year to US$291,000/year + bonus + equity + benefits
Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.
Equal Employment Opportunity Meta is proud to be an Equal Employment Opportunity employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, reproductive health decisions, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, political views or activity, or other applicable legally protected characteristics. You may view our Equal Employment Opportunity notice here. Meta is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures. If you need assistance or an accommodation due to a disability, fill out the Accommodations request form.
- Architecture exploration
- Micro-architecture development
- RTL development using Verilog, System Verilog and HLS
- Soft and hard IP identification, selection and integration
- Collaboration with verification and emulation teams in test plan development and debug
- Collaboration with the implementation team to close the design on timing and power
- Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
- 12+ years of experience in micro-architecture and RTL development for complex IPs or Subsystems
- Experience in leading the development of complex SOCs for datacenter applications
- Experience in leading chip development from Architecture to Tapeout
- Experience in data-path development
- Experience in CPU, Network protocols, NOC, Memory and Peripheral Subsystems
- Experience with Synthesis, Timing Closure and Formal Verification Methodology
- Master’s or PhD degree in Electrical Engineering, Computer Science or related areas
US$212,000/year to US$291,000/year + bonus + equity + benefits
Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.
Equal Employment Opportunity Meta is proud to be an Equal Employment Opportunity employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, reproductive health decisions, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, political views or activity, or other applicable legally protected characteristics. You may view our Equal Employment Opportunity notice here. Meta is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures. If you need assistance or an accommodation due to a disability, fill out the Accommodations request form.
ASIC Engineer, Design
Office
Sunnyvale, CA | Austin, TX
Full Time
212k - 291k USD/year
August 9, 2025