Analog/Mixed Signal Design Verification Intern
Allegro MicroSystems
Office
Prague, Czech Republic, Czechia
Full Time
The Allegro team is united by a clear purpose—advancing technologies that make the world safer, more efficient, and more sustainable. With over 30 years of experience in semiconductor innovation, we bring that purpose to life across every part of the business—from breakthrough product development and customer success to how we show up for each other and the communities we serve.
The Opportunity
Want to use your mixed-signal verification expertise to help create a safer, more sustainable world? At Allegro MicroSystems, we're developing sensor technologies that power innovation in automotive, industrial, and consumer electronics. Join our collaborative and supportive design team in Prague, where you'll have the flexibility to learn and grow in a dynamic environment. We offer flexible work hours in a friendly environment.
Launch your mixed-signal verification career with a challenging, rewarding, long-term, and paid internship at Allegro MicroSystems! Work alongside experienced engineers in our Prague Design Center, designing cutting-edge integrated circuit solutions used in the automotive industry!
What You Will Do
Learn how to verify complex Integrated Circuits using Mixed-Signal simulation techniques.
Understand how an integrated circuit works from system level down to transistor level
Get familiar with Integrated Circuits development process from specification to manufacturing
Gain practical experience with industry-standard mixed-signal verification tools, including Cadence AMS Designer.
Develop test benches and test cases to verify compliance of the design with the specification
Collaborate on real-life projects with teams spread worldwide
Potential to complete your Diploma Thesis with us under the supervision of skilled engineers.
Who You Are
Curious about mixed-signal verification and a desire to learn and grow.
Foundational understanding of analog and digital design principles.
Basic knowledge of a mixed-signal modeling language like Verilog-AMS, SystemVerilog or VHDL-AMS.
Communication and teamwork skills.
We welcome applications from students in their Master's program.
Analog/Mixed Signal Design Verification Intern
Office
Prague, Czech Republic, Czechia
Full Time
August 7, 2025